An alliance led by IBM Research has produced the semiconductor industry’s first 7nm node test chips with functioning transistors. The breakthrough, accomplished in partnership with Globalfoundries and Samsung at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering, could result in the ability to place more than 20 billion tiny switches, that means transistors, on the fingernail-sized chips that power everything from smartphones to spacecraft.
Michael Liehr and Bala Haranand with a wafer comprised of 7nm chips. (Darryl Bautista/Photo Service IBM)
To achieve the higher performance, lower power and scaling benefits promised by 7nm technology, researchers had to bypass conventional semiconductor manufacturing approaches. Among the novel processes and techniques pioneered by the IBM Research alliance were a number of industry-first innovations, most notably Silicon Germanium (SiGe) channel transistors and Extreme Ultraviolet (EUV) lithography integration at multiple levels.
Industry experts consider 7nm technology crucial to meeting the anticipated demands of future cloud computing and Big Data systems, cognitive computing and mobile products. Part of IBM’s $3 billion, five-year investment in chip R&D, this accomplishment was made possible through a unique public-private partnership with New York State and joint development alliance.
“For business and society to get the most out of tomorrow’s computers and devices, scaling to 7nm and beyond is essential,” said Arvind Krishna, senior vice president and director of IBM Research. “That’s why IBM has remained committed to an aggressive basic research agenda that continually pushes the limits of semiconductor technology. Working with our partners, this milestone builds on decades of research that has set the pace for the microelectronics industry, and positions us to advance our leadership for years to come.”
The alliance achieved close to 50 % area scaling improvements over today’s most advanced technology. These techniques and scaling could result in at least a 50 % power/performance improvement for next generation mainframe and power systems that will improve today’s and power emerging technologies.
